cxl

5 stories

Stories

Topic: cxl

ScaleFlux bets its controller chips can break AI’s memory bottleneck
AI data centers have spent heavily on faster accelerators, denser racks and liquid cooling to keep that hardware running. The data pipeline that feeds those processors has not kept up, and expensive compute ends up waiting on memory and storage.
SiliconANGLEOct 15, 20263 min read
Open specs could cut AI data center hardware integration from a year to months
As AI factories scale, hardware interoperability is becoming as important as raw performance. Accelerators, memory and storage now come from many different suppliers, and every mismatch between them slows deployment across the data center.
SiliconANGLEOct 14, 20264 min read
Marvell Structera X 3406 and 3506 CXL 3.2 Memory Expanders
The new Structera X 3406 and Structera X 3506 offer six channels and up to 18 DIMMs per controller for CXL 3.2 memory expansion The post Marvell Structera X 3406 and 3506 CXL 3.2 Memory Expanders appeared first on ServeTheHome.
ServeTheHome Deep LearningOct 12, 20262 min read
Astera Labs’ Leo Controller Update Targets Memory Constraints
Astera Labs pairs Leo memory controllers with Scorpio fabric switches to bring scalable memory closer to AI accelerators. The post Astera Labs’ Leo Controller Update Targets Memory Constraints appeared first on EE Times.
EE TimesSep 29, 20265 min read
Xcena Cuts Data Movement to Address Memory Bottlenecks
Xcena’s MX1 uses CXL to push compute into memory by combining DDR5, SSDs, and RISC-V cores while easing programmability. The post Xcena Cuts Data Movement to Address Memory Bottlenecks appeared first on EE Times.
EE TimesSep 28, 20264 min read